// Etienne Sicard
// Test Verilog with complex gates
// 10 May 2002

module vlgBenchComplex(c1,c2,c3,g0,g1,g2,p0,p1,p2,c0);
  input g0,p0,c0;
  input g1,p1;
  input g2,p2;
  output c1,c2,c3;

// carry look ahead adder
  assign c1=g0|(p0&c0);
  assign c2=g1|(p1&(g0|(p0&c0)));
  assign c3=g2|(p2&g1)|(p2&p1&g0)|(p3&p2&p1&g0);

endmodule


